当然作为入门实验的流水灯实验是很简单的。基本没有什么可操作性

但是为了完整性,我也试着写了一个简单的。

module ledflow(

  input clk,

  input rst_n,

  output [7:0] leds

);

reg [7:0]leds_r;

assign leds = leds_r;

reg [24:0] clk_cnt_r;

reg en_leds_r;

reg [7:0]ledstate;

parameter leddata0 = 8'b1111_1110,

                leddata1 = 8'b1111_1101,

      leddata2 = 8'b1111_1011,

      leddata3 = 8'b1111_0111,

      leddata4 = 8'b1110_1111,

      leddata5 = 8'b1101_1111,

      leddata6 = 8'b1011_1111,

      leddata7 = 8'b0111_1111;

/17D7840 = 25M

always @ (posedge clk or negedge rst_n)

  if(!rst_n)

   clk_cnt_r <= 25'd0;

 else

  begin

   clk_cnt_r <= clk_cnt_r + 1'b1;

   case(clk_cnt_r)

   25'h17D7840 : begin clk_cnt_r <= 25'd0; en_leds_r <= 1'b1; end

   default           : en_leds_r <= 1'b0;

 endcase

 end

always @ (posedge clk or negedge rst_n)

  if(!rst_n)

    begin

    leds_r <= 8'b0000_0000;

  ledstate <= leddata0;

  end

  else

   begin

    if(en_leds_r)

     begin

     case(ledstate)

     leddata0 : begin  leds_r <= leddata0; ledstate <= leddata1; end

   leddata1 : begin  leds_r <= leddata1; ledstate <= leddata2; end

   leddata2 : begin  leds_r <= leddata2; ledstate <= leddata3; end

   leddata3 : begin  leds_r <= leddata3; ledstate <= leddata4; end

   leddata4 : begin  leds_r <= leddata4; ledstate <= leddata5; end

   leddata5 : begin  leds_r <= leddata5; ledstate <= leddata6; end

   leddata6 : begin  leds_r <= leddata6; ledstate <= leddata7; end

   leddata7 : begin  leds_r <= leddata7; ledstate <= leddata0; end

   default   : begin  leds_r <= 8'b11111111;ledstate<=leddata0;end

  endcase

   end

 end

endmodule

程序也是很简单的。  

但是中间的调试竟然也是花了我一点时间。

本程序也让我通过AS下载到了配置芯片中,从而是上电后会进行相应的配置。